Production testing of semiconductor integrated circuits, also referred to as “chips” herein, requires that not only devices which fail solidly be identified and dealt with, but also devices which operate marginally, i.e., those whose operation is near failing. It is common for marginal devices to be taken offline and replaced with devices which test good in order to avoid them failing later when a more costly repair would be required. Alternatively, marginal devices can be allowed to remain a part of the operating configuration, provided that the chip is appropriately tagged and the marginality of its devices are identified to downstream users which incorporate the marginal chip into further equipment. Stated another way, some chips which operate satisfactorily under certain restricted conditions, e.g., less frequent use, shorter lifetime, shorter power-on-time per day, or under better controlled temperatures, but which are likely to fail outside of such conditions may nevertheless be usable if tagged as being marginal and restricted to such use or uses.
Semiconductor memories include particular devices that are subject to variation in operating characteristics, such as due to unavoidable non-uniformities in the processing of the devices. This is particularly true of dynamic random access memories (“DRAMs”), because the design of DRAMS tends to favor the optimization of circuit density and cost. Such variations can cause some of the millions (or even billions) of memory cells of a DRAM to either fail at the time of production test, or to operate marginally at that time. Unfortunately, to downstream equipment which incorporates the chip, marginally operating memory cells can inflict greater harm than those which fail solidly during initial testing. Frequently, the marginally operating memory cell will fail hard later during the expected lifetime of the DRAM. However, today's expectations of long-term equipment reliability and performance are adverse to memory cell failures which occur later during the useful lifetime of the equipment. Even if only one of the marginal memory cells of the DRAM fails later on, reliability and performance are impacted in ways that are not acceptable to the end user.
Therefore, to assure the long-term reliability and usability of the chip, marginally operating memory cells as well as failing memory cells must be removed from the configuration at the time of production testing. Marginally operating memory cells and failing memory cells are typically replaced with redundancy memory cells available on the chip. In this way, the DRAM remains addressable by devices external to the DRAM as one intact unit offering storage and retrieval of data over one continuous address space.
On the other hand, sometimes a large number of the memory cells of a DRAM chip exhibit the same degree of marginality. If the degree of marginality is not too extreme, for example, the refresh interval must be set to 64 ms instead of 128 ms, such marginality may be deemed to be acceptable when the particular chip is tagged and used for a particular purpose that is not considered to be “mission critical.” In such case, the large number of marginal memory cells make redundancy replacement impractical or impossible; however, the degree of the marginality is considered acceptable for the particular purpose for which the chip is used. In a third case, both the number of marginal memory cells and their degree of marginality are so great that it is impractical to repair or use the chip as a marginally performing chip. In such case, the chip is identified to be scrapped.
Of course, the problem is how to identify and characterize marginally operating memory cells such that an informed decision can be made whether the marginal memory cells should be repaired and replaced with tested good redundancy cells, instead of being tagged and sold as a marginal chip, or otherwise scrapped.
It has been estimated that a single-bit failure is the most prevalent type of defect in a DRAM. Redundancy replacement designs of DRAMs typically allow a prevalence of single bit failures of up to about 1%. Single-bit failures frequently result from variations in the manufacturing process which affect either the capacitance of the storage capacitor element of the DRAM cell, or cause leakage current off the DRAM cell to exceed limits. While such failures are frequently manifested during production testing under standard operating conditions, more severe test conditions are required to investigate marginal DRAM cells.
Many DRAMs include memory cells or “DRAM cells” which have only one capacitor and one transistor, the transistor being used as a passgate device or “pass-gate transistor” for controlling the reading and writing of the DRAM cell.
In a DRAM cell a datum is stored as a charge on the storage capacitor. The pass-gate transistor is turned on to write the datum to the DRAM cell, and to read the datum that is stored in the DRAM cell. Because the datum is stored as a charge on a capacitor, it has a tendency to weaken over time due to a small amount of current that inexorably flows off of the capacitor as “leakage current”. For that reason, DRAM cells require periodic refreshing to restore, i.e. “recharge” the stored charge in the DRAM cell to a desirable level to maintain signal margin. However, not all DRAM cells of a DRAM can store a given amount of charge for the same time interval. Some DRAM cells which have relatively large leakage currents must be refreshed at more frequent intervals than other DRAM cells. It is the identification and characterization of such cells having larger leakage currents that needs to be performed better at time of production testing.
A particularly promising way of performing such testing of DRAM cells is by performing “write-window” testing. A “write-window” test seeks to identify and characterize marginal memory cells of a DRAM by varying the electrical operating conditions for reading and writing memory cells to a point which stresses the ability of the memory cells to retain stored data between successive refresh intervals.
In a “write-window” test, the time interval allotted to write a datum into a memory cell is shortened. This results in a smaller amount of charge being stored on the capacitor element of the memory cell than during normal operation. If the memory cell is then read after the refresh interval (or longer predetermined period of time) has passed, the faithfulness or lack thereof displayed by the memory cell in retaining the stored datum indicates whether the memory cell passes or fails during the stressed operating condition defined by the shortened writing interval.
In performing such “write-window” testing, it is desirable to test using a range of shortened writing intervals, in order obtain results having desirable granularity. Heretofore, it has not been possible to achieve a desired level of granularity when using available external test equipment to test advanced DRAM chips. Problems of attempting such testing are best illustrated with reference to the prior art organization of a DRAM shown in FIG. 1, and an illustrative prior art timing diagram provided in FIG. 2.
FIG. 1 illustrates an internal organization of a DRAM 100 which includes a DRAM array 102 having memory cells disposed at the intersections of wordlines 104 and bitlines 106. The wordlines of the DRAM array 102 are operated (“accessed”) by wordline driver (WL DRV) circuitry 108, a particular driver of which is selected by row decoder (ROW DEC) circuitry 110. Data is read from or written to memory cells on an accessed wordline of the array 102 via the bitlines 106, as latched from, or driven by sense amplifier and precharge circuitry (SA/PCHG) 112, respectively. SA/PCHG 112 also functions to precharge, i.e., reset to a predetermined voltage, the bitlines between accesses of wordlines. In this way, signals that are read from or written to the memory cells when wordlines are accessed will transition in predictable ways. The SA/PCHG 112 exchanges read or write data with an external data input/output interface 114 of the DRAM 100 through second sense amplifier circuitry (SSA) 116. SSA 116 functions to transfer a typically limited set of data bits on a selected column or set of columns with the SA/PCHG 112, the limited set of data bits being determined by a column address (COL ADDR) provided to a column decoder (COL DEC) 118. Similarly, a row address (ROW ADDR) provided to the row decoder 110 determines the particular wordline to be accessed during a given memory access cycle. The column address and the row address are typically provided from an address bus or address control interface which may include column predecoder circuitry and row predecoder circuitry, as incorporated in the element referenced in FIG. 1 as address control element 120.
A controller 122 generates many of the control signals needed to operate the DRAM including a column address strobe (CAS) signal which times the operation of the column decoder 118 and a row address strobe (RAS) signal which times the operation of the row decoder 110. Typically, the controller 122 also controls operation of the DRAM 100 to refresh the memory cells of the DRAM array 102 by providing a number “y” of control signal lines to the address control element 120 for controlling which addresses of the DRAM array 102 are presented to be refreshed, as well as the timing and control of the presentation of addresses for reading, writing refreshing the DRAM array 102. In addition, the controller 122 may also provide an autoprecharge timing signal (“APCHG”), which is timed in relation to the beginning of a DRAM read or write cycle (for example, as timed in relation to the RAS signal or WL_EN signal that the controller generates to time wordline decoding and driving operations). Such autoprecharge timing signal times the beginning of the bitline precharge interval to generally or closely coincide with the time that the accessed wordline is deactivated. For example, the autoprecharge timing signal is designed to begin the precharging of the bitlines at the same time that the accessed wordline is deactivated; i.e., “de-selected,” as by disabling the WL_EN signal. In addition to the autoprecharge timing signal, the controller 122 outputs a select (SEL) signal for selecting between an external precharge timing signal (PCHG) and the autoprecharge timing signal (APCHG) generated by the controller 122. Using the autoprecharge timing, the bitline precharging operation begins at a fixed interval of time after a particular wordline is activated using the WL_EN signal. By contrast, the external precharge signal (PCHG), arriving from external circuitry, e.g., external test equipment, is not so constrained. The external precharge signal PCHG can be timed to transition at various times, all depending upon the capability of the external test equipment and the fidelity of the signal channel from the test equipment into the DRAM 100 on the chip. However, there is a problem in that getting PCHG to transition at desired timings poses insurmountable challenges, as will become apparent in the following.
FIG. 2 will now be described as an example of difficulties encountered when write-window testing is attempted using available external test equipment. In one way of performing write-window testing, a datum is “strongly” written to a memory cell at one logic level, e.g., logic “LOW” or logic “0”. Subsequently, a datum having the opposite logic level, e.g., logic level “HIGH” or logic “1”, is written to the same memory cell. Then, the prescribed interval for refreshing the memory cell is allowed to pass, after which the memory cell is then read. The act of weakly writing the “1” can be performed by shortening the active duty cycle of the wordline for that write operation. Curve 150 of FIG. 2 illustrates a voltage level on a wordline of the prior art DRAM array 100 shown in FIG. 1. When the voltage level on the wordline is low, the wordline is not active, such that the passgate transistors of the memory cells connected to that wordline are turned off and the memory cells are not accessed at that time. On the other hand, when the voltage level on the wordline is high, the wordline is activated such that the pass-gate transistors of the memory cells connected thereto are turned on, and those memory cells are then accessed. At such time that the wordline voltage level is high, charge stored on capacitors of the memory cells begins to flow out of the capacitors onto the bitlines connected to each of the memory cells.
During normal operation, at time 152, the voltage on the wordline transitions from the low, inactive level to the high, active level. After the wordline is activated, the memory cells connected to that wordline can then be read, written or refreshed, the reading operation combining the latching and outputting the read data to SSA 116 (and on to the data I/O interface 114 (FIG. 1)), as well as refreshing all the memory cells connected to the wordline. At a later time 154, the wordline transitions again from the high voltage level to low voltage level. At that time, the memory cells are blocked from access, and the charge stored on the capacitors thereof is maintained until the next wordline access. This is followed by at least a minimum interval of time 156 required to precharge the bitlines of the DRAM 100 prior to the next activation of the same wordline. During such “precharge interval” 156, the voltages on non-accessed bitlines are reset to a predetermined voltage.
Thereafter, at a time 158, the DRAM is controlled to write a “0” to a memory cell. Preferably, the “0” is “strongly” written to the memory cell, i.e., written in a way which normally results in the voltage stored on the capacitor reaching the desired logic level. As shown in FIG. 2, at time 158, the wordline transitions to the active, high voltage level and a “0” is written to a memory cell that is accessed by the activated wordline. Once the “0” has been written the voltage level, the wordline is again lowered to the low voltage level at time 160. In order to “strongly” write the memory cell, the writing operation represented by the interval of time between times 154 and 160 can be repeated one or more times at the same logic “0” level after the initial writing operation.
Thereafter, at a later time 162 during operation, the memory cell is written to the logic “1”, i.e., the high level. However, this time, the writing operation is conducted using a shortened time interval for activating the wordline, ending at time 163, such that the “1” is only weakly written to the memory cell. Then, the accessed wordline is again deactivated. In order to test the memory cell under a fully stressed condition, the wordline is then maintained low for a period of time at least as long as the refresh interval tR, illustratively 128 ms, before being accessed again. The inactive period of time allows charge to escape from the capacitor of the memory cell via leakage current through any leakage paths which may be present. Thereafter, at time 164, the wordline is again activated and the contents of the memory cell are read therefrom.
At this time, when the memory cell tests good, the value of the datum read from the memory cell remains “1”, despite the stressed conditions under which the “1” is initially written to the memory cell, and the long interval of time that elapses before reading the memory cell again. However, if the memory cell is one that performs marginally or fails under normal conditions, the value in the memory cell might appear as a “0” instead when read. In such way, the marginal or failing memory cell is identified through the write-window test.
However, as noted above, one goal of testing is to determine with sufficient granularity the stressed conditions under which memory cells fail. Available external test equipment does not satisfy this goal. Curve 170 illustrates a waveform input to a time demultiplexer 124 of DRAM 100 (FIG. 1) for controlling the timings at which wordlines of the DRAM 100 are activated, and a precharge control signal PCHG is applied to SA/PCHG 112 to precharge the wordlines in between activations of the wordlines. Referring to FIG. 2, the period to of the waveform between the rising edge of the WL_EN (wordline enable) signal and the PCHG (external precharge timing signal) defines the period for maintaining the wordline active.
Unfortunately, owing either to the external test equipment or the quality of the interface to the chip or both, the quality of the signal waveform 170 input to the DRAM 100 from the external test equipment is poor. This precludes this arrangement from providing adequate granularity in write-window testing. Pulse 172 of waveform 170 illustrates this point. The signal waveform arriving at demultiplexer 124 (FIG. 1) has a rise time or “transition time” tT of approximately 20 ns and jitter tJ of about 10 ns. The transition time tT and the jitter tJ make the signal edges and duration of the WL_EN signal imprecise. While it is desired to vary the length of the wordline activation interval tW in 1 ns increments over a 20 to 30 ns range for write-window testing, the large jitter and long transition time according to the prior art arrangement shown in FIG. 1 preclude such testing from being performed.
Accordingly, a new DRAM circuit and method are desired which are capable of providing write-window testing with greater granularity than that provided heretofore according to the prior art.